The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.
While features of integrated circuits (ICs) shrink, modeling the impact of physical and layout effects in IC designs is needed. For example, process design kits (PDKs) or process access kits (PAKs) have been commercially employed to build up ICs in efforts to increase density on a wafer and model locations of components on the wafer. Generally. PDKs include geometric descriptions and models of devices, such as transistors, diodes, resistors, capacitors, etc. Conventionally, circuit design engineers translate PDKs to transistor netlists and/or gate-level netlists for circuit simulations. Based upon the simulation results, circuit design engineers can then predict and/or modify the designs of the ICs.
In advanced processes such as, but not limited to, a 28 nanometer (N28) process, a 20 nanometer (N20) process, and the like, device performance is impacted by physical layout structure and surrounding environment effects such as a density gradient, edge and layout dependent effects. Conventionally, these layout related impacts are guessed or estimated in the simulation phase prior to actual layout of circuitry.